B.Tech EEE · NIT Karnataka, Surathkal · Class of 2027

Mitukula Saivarshith

Final-year (4th year) EEE student at NIT Karnataka (graduating 2027) passionate about digital system design, RTL verification, and mixed-signal circuits. I build processors in Verilog, simulate power converters in LTspice, and characterize CMOS cells with open-source PDKs.

8.56 CGPA

#1700 HDLBits Rank

3.18× Pipeline Speedup

1.57 CPI (RV32I)

View Projects GitHub

// 01. about

About Me

I'm a final-year (4th year) Electrical & Electronics Engineering student at NIT Karnataka, Surathkal (Aug 2023 – 2027), maintaining a CGPA of 8.56. My work sits at the intersection of digital hardware and low-level software — from designing synthesizable RISC-V pipelines in Verilog to characterizing CMOS cells using the open-source SKY130 PDK.

During my internship at URSC, ISRO, I designed and verified a wide-range buck converter achieving a 1.84 mV worst-case output ripple — benchmarked against space-grade PMICs. I enjoy the full design loop: spec → RTL → simulation → verification.

Outside the lab I lead Tronix, the technical club at NITK, and hold a global rank of #1700 on HDLBits.

Education

National Institute of Technology Karnataka, Surathkal

B.Tech — Electrical & Electronics Engineering | Aug 2023 – 2027 (Expected)

CGPA: 8.56

Sri Chaitanya Institutions

Intermediate Course (PCM) | Jun 2021 – Apr 2023

Percentage: 90.7%

// 02. projects

Technical Projects

Verilog HDL · Jun 2026

5-Stage Pipelined RV32IM RISC-V Processor

Verilog HDL Icarus Verilog GTKWave RISC-V

Designed IF–ID–EX–MEM–WB pipelined RV32I processor with EX/MEM forwarding, load-use hazard detection, and branch stall resolution in pure Verilog-2001.
Integrated 2-level L1/L2 cache hierarchy interface backed by synchronous SRAM, with stall/flush-controlled pipeline registers.
Verified via self-checking Icarus Verilog testbenches and GTKWave waveforms.

CPI 1.57 3.18× Speedup

Verilog HDL · Jul 2025

10-Bit Frame UART Transmitter-Receiver

Verilog HDL FSM Icarus Verilog GTKWave

Full-duplex UART transceiver in Verilog HDL with a 10-bit frame FSM and middle-bit sampling logic for accurate frame reception.
Configurable baud rate, 3 parity modes (odd/even/none), and 3-way error detection (parity, start, stop bit).
16× oversampling in the receiver for accurate bit-level data recovery from serial input.

SKY130 PDK · Mar 2026

CMOS Circuit Design & SPICE Simulation

SKY130 PDK SPICE CMOS ngspice

Characterized SKY130 NMOS short-channel I_D–V_DS curves across operating regions, incorporating velocity saturation effects.
Derived CMOS inverter VTC — voltage gain improved from 7.47 to >15 upon V_DD scaling (1.8V → 0.8V).
Optimized PMOS/NMOS sizing (1×–5×): rise delay cut from 148 ps → 37 ps; NMH = 0.736 V, NML = 0.656 V.

MATLAB / Simulink

SPWM Cascaded H-Bridge Multilevel Inverter

MATLAB Simulink Power Electronics

Designed and evaluated an SPWM-based cascaded H-bridge multilevel inverter to enhance power quality through harmonic reduction.
Simulated 3-level and 5-level topologies; achieved significant THD improvement across configurations.
Delivered 34.05 V RMS output from a 100 V DC input with low distortion.

// 03. experience

Experience & Leadership

Summer Research Intern — U.R. Rao Satellite Centre (URSC), ISRO

Bengaluru, India | May 2026 – Jun 2026

ISRO LTspice

Designed and verified a wide-input (11V–42V to 5V, 4A) buck converter in LTspice, implementing closed-loop voltage-mode PWM control at 100 kHz to achieve tight line regulation and a 1.84 mV worst-case output ripple.
Optimized LC filter components (600 µH, 50 µF) through parametric transient simulations and benchmarked performance against the space-grade TI TPS7H5001-SP PMIC architecture.

Convener — Tronix, NITK

Led the technical fest club by organizing events, workshops, and student engagement initiatives.

Event Lead — EESA Day 2026, NITK

Managed planning and execution of the EEE department's flagship annual event, coordinating volunteers, logistics, and stakeholder communication.

PR Team — HackVerse 5.0, NITK

Coordinated participant outreach and managed stakeholder communication for the national-level hackathon.

// 04. skills

Technical Skills

Languages

C Verilog HDL Python

MCUs / CPUs

ARM7TDMI RISC-V Arduino

Tools

Icarus Verilog GTKWave MATLAB Simulink LTspice VS Code

Technologies

RTL Design SKY130 PDK

Practice

HDLBits — Rank #1700

// Relevant Coursework

Digital Electronics
Design of Digital ICs
Computer Organization & Architecture
Hardware Modeling using Verilog HDL